1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to an NAND type non-volatile ferroelectric memory cell and a non-volatile ferroelectric memory of the same.
2. Background of the Related Art
FIG. 1 illustrates a system of a related art NAND type DRAM.
Referring to FIG. 1, the NAND type DRAM cell is provided with a plurality of NMOS transistors T1, T2, T3, - - - connected in series, each having a gate connected to a wordline WL1, WL2, WL3, WL4, - - - . There is a bitline B/L formed in a direction crossing the wordlines, and there are ferroelectric capacitors C1, C2, C3, - - - each having one electrode connected to a drain terminal N1, N2, N3, - - - of the transistor and the other electrode connected to a plateline P/L, on which a constant voltage of xc2xd voltage is provided. Upon enabling the wordlines WL1, WL2, WL3, - - - in succession, NMOS transistors connected thereto are enabled, to provide data stored in the ferroelectric capacitors to the bitline. The data provided to the bitline is amplified at a sense amplifier(not shown), and re-stored in the ferroelectric capacitor.
The ferroelectric memory, i.e., an FRAM(Ferroelectric Random Access Memory), having in general a data processing speed similar to a DRAM(Dynamic Random Access Memory) used widely as a semiconductor memory and being capable of conserving data even if the power is turned off, is paid attention as a next generation memory. The FRAM, a memory having a structure similar to the DRAM, is provided with a capacitor of a ferroelectric material for utilizing a high residual polarization of the ferroelectric material. The residual polarization permits the conservation of a data even after removal of an electric field.
FIG. 2 illustrates a characteristic curve of a hysteresis loop of a general ferroelectric material.
Referring to FIG. 2, it can be known that a polarization induced by an electric field is, not erased, but, certain amount(xe2x80x98dxe2x80x99 and xe2x80x98axe2x80x99 states) of which is remained, even if the electric field is removed owing to existence of the residual polarization(or spontaneous polarization). The xe2x80x98dxe2x80x99 and xe2x80x98axe2x80x99 states are corresponded to xe2x80x981xe2x80x99 and xe2x80x980xe2x80x99 respectively in application to memories.
A related art non-volatile ferroelectric memory will be explained with reference to the attached drawings. FIG. 3 illustrates a system of unit cell of the related art non-volatile ferroelectric memory.
Referring to FIG. 3, the system of unit cell of the related art non-volatile ferroelectric memory is provided with a bitline B/L formed in one direction, a wordline W/L formed in perpendicular to the bitline, a plateline P/L formed spaced from the wordline in a direction identical to the wordline, a transistor T1 having a gate connected to the wordline and a source connected to the bitline, and a ferroelectric capacitor FC1 having a first terminal connected to a drain of the transistor T1 and a second terminal connected to the plateline P/L.
A circuit for driving the related art ferroelectric memory will be explained. FIGS. 4A and 4B illustrate a circuit for driving the related art nonvolatile ferroelectric memory.
The circuit for driving the related art ferroelectric memory of an 1T/1C(one transistor and one ferroelectric capacitor) structure is provided with a reference voltage generator 1 for generating a reference voltage, a reference voltage stabilizer 2 having a plurality of transistors Q1xcx9cQ4 and a capacitor C1 for stabilizing reference voltages on adjacent two bitlines, a first reference voltage storage 3 having a plurality of transistors Q6-Q7, and capacitors C2-C3 for respectively having logical values of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d stored in adjacent bitlines, a first equalizer 4 having a transistor Q5 for equalizing adjacent two bitlines, a first main cell array 5 connected to wordlines and platelines different from each other for storing data, a first sense amplifier 6 having a plurality of transistors Q10xcx9cQ15, a P-sense amplifier PSA and the like for sensing data in cells selected by the wordline among the plurality of cells in the first main cell array 5, a second main cell array 7 connected to wordlines and platelines different from one another for storage of data, a second reference voltage storage 8 having a plurality of transistors Q28xcx9cQ29 and capacitors C9xcx9cC10 for having reference voltages with logical values of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d stored in adjacent bitlines, and a second sense amplifier 9 having a plurality of transistors Q16xcx9cQ25, N-sense amplifier NSA and the like for sensing and forwarding a data in the second main array 7.
The data input/output operation of the related art ferroelectric memory will be explained. FIG. 5 illustrates a timing diagram of a write mode operation of the related art ferroelectric memory, and FIG. 6 illustrates a timing diagram of a re ad mode operation of the related art ferroelectric memory.
In writing, when an external chip enable signal CSB pad is enabled from xe2x80x98highxe2x80x99 to xe2x80x98lowxe2x80x99 and a write enable signal WEBpad is applied from xe2x80x98highxe2x80x99 to xe2x80x98lowxe2x80x99 on the same time, the write mode is started. When address decoding is started in the write mode, a pulse applied to a pertinent wordline is transited from xe2x80x98lowxe2x80x99 to xe2x80x98highxe2x80x99 to select a cell. Thus, during a period the wordline is held xe2x80x98highxe2x80x99, a pertinent plateline has a xe2x80x98highxe2x80x99 signal applied thereto for one period and a xe2x80x98lowxe2x80x99 signal applied thereto for the other period in succession. And, in order to write a logical value xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99 on the selected cell, a xe2x80x98highxe2x80x99 or xe2x80x98lowxe2x80x99 signal synchronized to the write enable signal WEBpad is applied to a pertinent bitline. That is, if a xe2x80x98highxe2x80x99 signal is applied to the bitline and a signal applied to the plateline is xe2x80x98lowxe2x80x99 in a period in which a signal applied to the wordline is xe2x80x98highxe2x80x99, a logical value xe2x80x981xe2x80x99 is written on the ferroelectric capacitor. And, if a xe2x80x98lowxe2x80x99 signal is applied to the bitline and a signal applied to the plateline is xe2x80x98highxe2x80x99, a logical value xe2x80x980xe2x80x99 is written on the ferroelectric capacitor.
The operation for reading the data stored in the cell by the aforementioned write mode operation will be explained.
If the chip enable signal CSBpad is enabled from xe2x80x98highxe2x80x99 to xe2x80x98lowxe2x80x99 externally, all bitlines are equalized to a xe2x80x98lowxe2x80x99 voltage before a pertinent wordline is selected. That is, referring to FIGS. 3A and 3B, if a xe2x80x98highxe2x80x99 signal is applied to the equalizer 4 and a xe2x80x98highxe2x80x99 signal is applied to the transistors Q18 and Q19, as the bitlines are grounded through the transistor Q19, the bitlines are equalized to a low voltage Vss. And, the transistors Q5, Q18, and Q19 are turned off, to disable the bitlines, an address is decoded, and the decoded address causes a xe2x80x98lowxe2x80x99 signal on a pertinent wordline to transit to a xe2x80x98highxe2x80x99 signal, to select a pertinent cell. A xe2x80x98highxe2x80x99 signal is applied to the plateline of the selected cell, to break a data corresponding to a logical value xe2x80x981xe2x80x99 stored in the ferroelectric memory. If a logical value xe2x80x980xe2x80x99 is in storage in the ferroelectric memory, a data corresponding to the logical value xe2x80x980xe2x80x99 is not broken. The data not broken and the data broken provide values different from each other according to the aforementioned hysteresis loop, so that the sense amplifier senses a logical value xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99. The case of the data broken is a case when the value is changed from xe2x80x98dxe2x80x99 to xe2x80x98fxe2x80x99 in the hysteresis loop of FIG. 2, and the case of the data not broken is a case when the value is changed from xe2x80x98axe2x80x99 to xe2x80x98fxe2x80x99 in the hysteresis loop of FIG. 2. Therefore, if the sense amplifier is enabled after a certain time period is passed, in the case of the data broken, a logical value xe2x80x981xe2x80x99 is provided as amplified, and in the case of the data not broken, a logical value xe2x80x980xe2x80x99 is provided. After the sense amplifier provides data thus, since an original data should be restored, the plateline is disabled from xe2x80x98highxe2x80x99 to xe2x80x98lowxe2x80x99 in a state a xe2x80x98highxe2x80x99 signal is applied to a pertinent wordline.
The aforementioned related art ferroelectric memory has the following problem.
The frequent use of one reference cell required for reading main cells a few hundred times more than the main cells under a state the ferroelectric properties are not assured perfectly, that requires the reference cell much more operation than the main cells, causes a rapid degradation of the reference cell, resulting in a voltage instability, device operation characteristics deterioration, and short lifetime.
Accordingly, the present invention is directed to an NAND type non-volatile ferroelectric memory cell and a non-volatile ferroelectric memory of the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an NAND type non-volatile ferroelectric memory cell and a non-volatile ferroelectric memory of the same, in which numbers of access to a main cell and a reference cell are made the same, to maintain bitline induced voltages by the reference cell and by the main cell constant, for improving operation characteristics, minimizing a layout area, and permits a high density device integration.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the NAND type non-volatile ferroelectric memory cell includes an N number of transistors connected in series, a bitline having an input terminal of a first transistor and an output terminal of (N)th transistor among the N number of transistors connected thereto, wordlines respectively connected to gates of the transistors except the (N)th transistor, a WEC signal line connected to a gate of the (N)th transistor and adapted to have an enable signal applied thereto only in a write or re-store mode, and ferroelectric capacitors respectively connected both to the wordlines and output terminals of the transistors.
In other aspect of the present invention, there is provided an NAND type non-volatile ferroelectric memory including a global X decoder for controlling a plurality of global wordlines, an N number of transistors connected in series, a bitline having a source of a first transistor and a drain of (N)th transistor among the N number of transistors connected thereto, a WEC signal line connected to a gate of the (N)th transistor, wordlines respectively connected to gates of the transistors except the (N)th transistor, a cell array having a plurality of NAND type non-volatile ferroelectric memory cells each having a ferroelectric capacitor connected between a drain of one of the transistors except the (N)th transistor and one of the wordlines, a bitline controller disposed under the cell array for temporary storage of a data read from any cell selected from the cell array, and forwarding the data in writing and re-storing, a local X decoder for providing an enable signal for enabling the wordlines and the WEC signal, and a wordline driver for applying the wordline enable signal from the local X decoder to the transistors in sequence starting from the first transistor, and applying the WEC signal only in a write mode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.